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• Hardening of selected cells for Space requirements
  
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• Design implementation (VHDL) of a video cadence detector module and a motion vector controller
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• Project environment definition and set-up with root access for the whole NXP site.
• Close work with IC architects to define, generate and modify Verilog IC infrastructure IPs like register access network, bus interfaces, address converters, interrupt controllers and glue logic to meet project requirements.

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