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• Design modification (VHDL) to replace Xilinx FPGA memories and Fifos with Atmel's ASIC equivalent modules
• Implementation of PAD level and Boundary Scan
  
• System verification setup and run (ModelSim)
  
• Full System Synthesis (Synopsys) with Scan insertion
• Hardening of selected cells for Space requirements
  
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• Design implementation (VHDL) of a video cadence detector module and a motion vector controller
• Testbench implementation
  
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• Formal Verification (Spyglass)
  

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• Close work with IC architects to define, generate and modify Verilog IC infrastructure IPs like register access network, bus interfaces, address converters, interrupt controllers and glue logic to meet project requirements.

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